1. Field of the invention
The present invention relates to a sync detection circuit and, more particularly, to an improvement of an automatic frequency control circuit for controlling the frequency of the horizontal sync signal (also referred to as a H-sync signal).
2. Description of the Prior Art
Generally, a television receiver has a synchronous detector which detects whether or not the vertical synchronizing signal (also referred to as a V-sync signal) is generated at a predetermined frequency. Such a synchronous detector is disclosed, for example, in Japanese Utility Model Publication (unexamined) No. 98971/1985 published July 5, 1985 or in U.S. Pat. No. 3,878,336 issued Apr. 15, 1975 or in a SANYO's brochure No. 1431 for LA7620 entitled "Monolithic Linear Integrated Circuit". An example of the synchronous detector is illustrated in FIG. 1.
In FIG. 1, a video signal applied to a terminal 1 is transmitted to a sync separator 2 which separates from the video signal a V-sync signal and a H-sync signal. The V-sync signal is applied to an AND gate 9, and the H-sync signal is applied to an AFC (automatic frequency control) 3. In AFC 3, the phase of the H-sync signal from sync separator 2 is compared with that of the fly-back pulse from a horizontal deflection circuit 4, and a phase difference therebetween is applied to a voltage controlled oscillator 5. Thus, voltage controlled oscillator 5 generates a pulse signal having a frequency which is a multiple of the frequency of the H-sync signal. A horizontal frequency divider 6 divides the frequency of the pulse signal from the voltage controlled oscillator and provides a pulse signal having a H-sync frequency f.sub.H to H-deflection circuit 4, and also provides a pulse signal having a frequency 2f.sub.H to a vertical frequency divider 8 at a clock input thereof and to a clock input of a D flip-flop 7.
The V-sync signal is applied to AND gate 9 which also receives a signal from a Q terminal of R-S flip-flop 10. The S-terminal of R-S flip-flop 10 receives from terminal 14 of the vertical frequency divider 8 a HIGH level signal produced during a period between 224H and 296H (H is one horizontal sync period) so that AND gate 9 connected to the Q terminal of flip-flop 10 is enabled after 224H.
Therefore, under the synchronizing condition, that is when the V-sync signal from sync separator 2 is produced after 224H, the V-sync signal will pass through the AND gate 9 and it will be applied to the D terminal of D flip-flop 7. Then, in response to the clock signal of 2f.sub.H from H-frequency divider 6, D flip-flop 7 produces a reset pulse from its Q terminal which is used for resetting the V-frequency divider 8.
On the contrary, under the asynchronous condition, that is when the V-sync signal from sync separator 2 is not produced in a period between 224H and 296H, the V-frequency divider 8 will be self reset. Therefore, V-frequency divider 8 produces a HIGH level signal from terminal 15 after 296H, which is applied through OR gate 11 to the D terminal of D flip-flop 7. Therefore, D flip-flop 7 produces a reset pulse in response to the pulse from terminal 15.
As apparent from the above, under the synchronizing condition, V-frequency divider 8 will be reset by the V-sync signal obtained from sync separator 2, and under the asynchronous condition, V-frequency divider 8 will be self-reset by the pulse produced from V-frequency divider 8. When the V-frequency divider 8 is reset, it activates vertical deflection circuit 12 which thereupon produces a vertical deflection pulse.
According to the above arrangement, since R-S flip-flop 13 has its S terminal connected to terminal 15 which produces a HIGH level signal after 296H, and also has its R terminal connected to AND gate 9, R-S flip-flop 13 will be reset under the synchronizing condition and, it will be set under the asynchronous condition. Therefore, R-S flip-flop 13 detects the synchronizing and asynchronous conditions.
It is possible, for example, to use the result of the synchronizing detection for controlling the sensitivity of the AFC 3 in the following manner. When the synchronizing condition is detected, the control current of AFC 3 is reduced (it may be possible to reduce the resistance of the AFC filter). Thereupon, the sensitivity of AFC 3 will be reduced so that the noise signal will not be easily picked up. On the other hand, when the asynchronous condition is detected, the control current of AFC 3 is increased (it may be possible to increase the resistance of the AFC filter). Thereupon, the sensitivity of AFC 3 will be increased so that the response time of the AFC loop will be shortened to shorten the pull in time of the H-sync signal.
However, with such an arrangement, a problem arises during a signal absent condition which occurs when the broadcasting is finished with the television receiver being still on, or when the television receiver is switched to a non-broadcasting channel. Under such a condition, no V-sync signal will be produced from sync separator 2 and, therefore, AND gate 9 will continue to produce a LOW level signal. However, by the HIGH level signal produced from terminal 15 at 296H, R-S flip-flop 13 will be set to produce a HIGH level signal from its Q terminal indicating the asynchronous condition. Therefore, the sensitivity of AFC 3 will be undesirably increased under the signal absent condition. Thus, it may possibly happen that VCO 5 is caused to malfunction by the noise signal from sync separator 2 to oscillate at a very low frequency. In such a case, one cycle period of the pulses from H-frequency divider 6 will be prolonged to prolong the on period of the transistor. Thus, the transistor may be overloaded to emit heat. Also, in such a case, due to the frequency change of the H-sync signal, the flyback transformer may produce undesirable buzzing sound. Furthermore, the crest value of the flyback pulse may be undesirably increased thereby increasing the anode voltage of the cathode ray tube. This will result in the increase of the beam speed hitting on the cathode ray tube, thereby producing unfavorable X-rays from the cathode ray tube.